This invention pertains generally to memory devices and the testing thereof and more particularly to an integrated circuit memory device and method of testing the same.
As memory chips become larger, the testing time required to verify that data is being correctly stored and read has increased, often at an exponentially growing rate. In dynamic wafer scale integration, wherein a relatively large number of memory chips on a single wafer are tested and then interconnected to provide an operative device when power is first applied, the test time is particularly important.
Memory devices such as random access memories (RAMs) are commonly tested by applying signals of known logic levels to the memory cells and reading the signals out of the cells individually to determine whether they are of the proper level. In one commonly used test, known as the "walking ones and zeros test", a signal having a logic level of either one or zero is applied to one of the memory cells and signals of the opposite logic level are applied to the remaining cells. The signals are then read out of the cells individually and tested for the correct logic levels. This test must be repeated for each of the cells in the device, and the entire procedure is repeated with signals of the opposite levels. With a square array of n memory cells of a single bit, this test requires about 2 .times. (3n + n.sup.2) memory cycles. For example, a 4096 bit RAM operating at a 1 microsecond rate would require a test time of over 30 seconds, and a 16,384 bit memory would take over 8 minutes to test. Thus, it can be seen that the test time for a single RAM chip can be excessive, and when several hundred such chips on a wafer are tested sequentially, the test time is considerable.